The core of an integrated circuit (IC) uses a high quantity of transistors to perform the required logic functions. Because the quantity of transistors used is so high, even a small reduction in the transistor size can create a significant overall reduction in chip area. Size reduction in a transistor can be accomplished by several methods. One method simply reduces the longthwidth of the device. For example, the trend of length-widths has gone from 600 nanometers to 350 nanometers to 180 nanometer over the past few years. Another method of reducing transistor size is to reduce the thickness of the gate oxide portion of the transistor. A thinner gate oxide improves the resolution of the patterned circuit because it reduces the shadow cast from the gate oxide protruding above the substrate.
However, reductions in transistor size have subsequently increased the sensitivity of the transistor, thereby requiring a lower operating voltage, for example 1.8 volts maximum operating voltage. Yet the input/output (I/O) signals in the IC have remained at a higher range of about 3.3 volts. Hence, for essentially the first time, the I/O signal voltage exceeds the maximum allowable voltage the IC core can withstand. Because of the excessive I/O signal voltage, a demand arose for a high-to-low voltage buffer to reduce the voltage of a high logic signal.
By reducing the voltage of a high logic signal, an IC core can be designed for this lower maximum operating voltage. For example, a less sensitive portion of a circuit can use a high logic signal, for example 3.3 volts, and still communicate to a more sensitive portion of a circuit, e.g. the IC core, that can only withstand a reduced high logic signal, for example 1.8 volts. By operating at a lower maximum voltage, a portion of the circuit, e.g. the IC core, can be designed and manufactured to be more sensitive, with corresponding benefits of consuming less power, operating faster, and occupying less chip area. Consequently, a need exists for a voltage buffer circuit that will reduce the I/O signal voltage to a level that the IC core can withstand.
As shown in Prior Art FIG. 1, one version of a prior art voltage buffer circuit 100 comprises two inverters 102 of a complementary metal oxide semiconductor (CMOS) transistor configuration. To withstand the voltage 103 of the high input signal 104 and the voltage of the first power supply 106 when compared to the output voltage 108, the individual transistors 110 require a thick gate oxide 112. Unfortunately, the thick gate oxide is undesirable because it causes the device to have a longer propagation delay time (e.g., longer switching time), thereby consuming more power. The higher power consumption and the longer switching time are directly attributed to the circuit design using transistors with a thick gate oxide that require more power and time to activate and deactivate (e.g. switch from low to high and from high to low).
Prior Art FIG. 2 is a graph 200 of the performance of the prior art voltage buffer circuit 100. The graph 200 illustrates the voltage changes in the voltage buffer circuit 100 over time as input signal 202 changes from low logic level 204 to high logic level 206 and correspondingly, the output signal 208 changes from low logic level 210 to high logic level 212. The propagation delay time 207 is the time required for output signal 208 to react to the change in input signal 202. Technically, the propagation delay time 207 is the difference between: 1) the input signal 202 reaching the 50% point 203 of its voltage transition; and 2) the output signal 208 reaching the 50% point 205 of its voltage transition. Hence, for the prior art voltage buffer circuit illustrated in Prior Art FIG. 1, the propagation delay time is approximately 289 picoseconds (i.e., from approximately the 450 picosecond mark to approximately the 739 picosecond mark). Considering the limitations of the prior art voltage buffer circuit, an apparent need exists for a voltage buffer circuit with low power consumption and with low propagation delay time (e.g. faster switching speed).
The prior art attempted to satiate this need by reducing the gate oxide thickness for the transistors used in the voltage buffer circuit. Unfortunately, when thin gate oxide transistors were used in the prior art voltage buffer circuit, they degraded quickly and ultimately failed to operate within a short period of time. The failure was attributed to degradation of the oxide layer from the electrical field which was excessively high in comparison to the thin gate oxide. The excessive electrical field was theorized to have created trapped charges in the oxide layer, knocked out atoms from the oxide layer, and degraded the effective carrier mobility in the device. Consequently, the prior art thin gate oxide transistors failed to satisfy the need for a voltage buffer circuit with low power consumption and with low propagation delay time. Hence, a need exists for a robust voltage buffer circuit that can withstand the high I/O voltage and produce a low core voltage.
In summary, there exists a need for a high-to-low voltage buffer that will reduce the I/O signal voltage range to a level that the IC core can withstand. Additionally, there exists a need for the voltage buffer circuit to operate with low power consumption and with low propagation delay time (e.g. faster switching speed). Finally, a need exists for the same voltage buffer circuit to have a robust capability for managing the required voltage levels without a quick or significant degradation in performance.